The EXCLUSIVE-OR (XOR) and the EXCLUSIVE-NOR (XNOR) type of logic gates are utilized as basic building blocks in many digital integrated circuit (IC) designs. Thus, a significant amount of emphasis is placed on reducing the speed and size of a these logic gates so as to minimize the total size of the IC while enhancing the speed of operation. In other words, the smaller and faster the designer can make a logic gate, the more desirable.
In digital circuit design, complex functional gates are designed using basic gates like inverters, passgates, and also discrete transistors. Each of those may contribute a finite amount of delay to the total delay of the complex gate. The number of such basic gates an input has to propagate through is referred to as the number of gate levels. Worst case delays often result when the input must propagate through the largest number of gate levels. One way in which circuit designers can increase the speed of logic is by reducing the number of gate levels in the worst case signal path.
Current XOR and XNOR logic gate designs utilize a minimum of six transistors. Typically, input signals need to pass through two gate levels in order to propagate to the output. Thus, the total delay of the XOR/XNOR gate is established by these two gate levels. In addition, all six transistors are commonly utilized to perform the logical functions of the XOR/XNOR gate and therefore need to be large enough so as to reduce resistive loading to subsequent logic stages. In other words, in prior art designs all six transistors must be relatively large such that they determine the overall size of the XOR or XNOR gate.
As will be seen, the presently invented XOR and XNOR gates comprise four instead of six primary transistors for performing the gates' logical functions. Since only four large transistors are utilized, the overall size of the XOR and XNOR gates of the present invention are smaller than prior art gates. In addition, unlike prior art designs in which a signal must pass through two gate levels to get from the input to the output, the gates of the present invention XOR/XNOR are designed in such a way that signal propagation is only through a single gate level. Thus, a smaller, faster XOR/XNOR gate is realized.